Polycrystalline thin films are used in silicon (Si) thin films for improving electrical properties of the thin film. When silicon is deposited on a glass substrate, it may form a polycrystalline silicon (p-Si) thin film or an amorphous silicon (a-Si) thin film.
FIG. 1A depicts the in-plane structure of polycrystalline silicon and FIG. 1B depicts the in-plane structure of amorphous silicon. Silicon is generally polycrystalline at temperatures greater than about 600° C., but amorphous at temperatures less than about 600° C.
One example of a polycrystalline silicon thin film is shown in FIG. 2, which is a schematic of the structure of a thin film transistor (TFT) for an active matrix organic light emitting diode (OLED). TFTs are classified into p-channel metal oxide semiconductor TFTs and n-channel metal oxide semiconductor (NMOS) TFTs. The active matrix OLED of FIG. 2 is driven by a complementary metal oxide semiconductor (CMOS) device using both PMOS and NMOS TFTS, forming a channel in the silicon. As the crystallinity of the silicon increases, the mobility of electrons/holes also increases. Therefore, crystalline silicon is desired for highly integrated CMOS devices. In particular, high quality crystalline silicon is desired to create larger OLEDs.
To fabricate a high quality thin film for an OLED, such as that shown in FIG. 2, polycrystalline silicon having good electrical properties, and not amorphous silicon, is desired to yield a TFT having good electron mobility.
One method for fabricating a silicon thin film is illustrated in FIG. 4 and involves depositing a polycrystalline thin film on a glass substrate by plasma enhanced chemical vapor deposition. First, a glass substrate is provided in a vacuum chamber at step S2. A SiN/SiO2 buffer layer is then deposited on the glass substrate at step S4. Then, amorphous Si is deposited on the buffer layer at step S6. The amorphous Si is then crystallized into polycrystalline Si at step S8.
FIG. 3 illustrates various processes for crystallizing silicon into a polycrystalline silicon thin film. This crystallization process is identified as step S8 in FIG. 4. These crystallization processes are classified into high temperature polycrystalline silicon (HTPS) processes and low temperature polycrystalline silicon (LTPS) processes.
In HTPS processes, quartz substrates are used, and the Si is crystallized by furnace annealing at a temperature greater than 600° C. However, quartz substrates are expensive, making commercialization of the product difficult. Further, manufacture of larger quartz substrates is difficult, making HTPS processes impractical for larger light-emitting devices.
In LTPS processes, annealing is performed by various energy sources. For example, in solid phase crystallization (SPC), amorphous Si is crystallized by furnace annealing or rapid thermal annealing (RTA), much like the HTPS processes. However, these processes cause substrate deformation and are very time consuming. Also, in metal induced crystallization (MIC) or metal induced lateral crystallization (MILC), a metal is patterned on amorphous Si and then crystallized by RTA or furnace annealing. However, these processes cause current leakage in the TFT due to silicide formation and the reaction of Si with the silicide.
In super grain Si (SGS) processes, a SiN buffer layer is grown on amorphous Si. Metal seed is then grown on the buffer layer and annealed. After crystallization, the SiN buffer layer is removed by wet etching. SGS processes are advantageous because grain size can be adjusted or coarsened. However, the processes are complicated, and the properties of the Si may be affected by the wet etching.
Similarly, excimer laser annealing (ELA) processes and sequential lateral solidification (SLS) process are very time consuming and the use of lasers limits the fabrication of large light-emitting devices. In particular, the laser equipment used for crystallization in commercial ELA is not only expensive but also has inherent properties that make it difficult to form a large beam. Further, in ELA processes, grain size cannot be controlled, thereby limiting application of ELA processes.